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DA4

4 (High Voltage) D/A Outputs (±100 VDC)

The Digital-to-Analog (D/A) module DA4 provides 4 high-voltage independent D/A output channels with a maximum full-scale range of ±100 VDC at ±10 mA (max). Linearity/accuracy is ±0.15% FS range over temperature. The DA4 provides voltage control loop mode, which is programmable for the application.

The DA4 module includes extensive Background Built-in-Test (BIT). In addition to output signal read-back (wrap) capabilities, overloaded outputs are detected with automatic channel shut-down protection, and the results are displayed in a status word. DA4 also include D/A FIFO buffering for greater control of the output voltage and signal data. Once enabled and triggered, the D/A FIFO buffer accepts, stores, and outputs the voltage commands for applications requiring simulation of waveform generation (single or periodic). The output data command word is formatted as a percentage of the Full Scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.

 

Features
  • High-quality D/A conversion, 16-Bit/channel
  • Designed to meet the testing requirements of IEC 801-2 Level 2
  • Continuous background BIT
  • Automatic shutdown protection with the results displayed in a status word
  • Extended D/A FIFO buffering capabilities

Specifications
  • Resolution: 16-bit/channel for voltage command mode.
  • Output Format: Single-ended
  • Output Range: ±100 VDC (unipolar or bipolar); ranges are programmable in pairs.
  • Output Impedance: < 1 Ω
  • System Protection: Output is set to 0 V at reset or Power-On.
  • Linearity Error: ±0.15% FS range over temperature
  • Offset Error: ±100 mV
  • Gain Error: ±0.08% FS range
  • Settling Time: 350 µs (max.)
  • Data Buffer: See Operations Manual for details.
  • Load: Can drive a capacitive load of 0.1 µF, 10 mA/Ch max. (Source or Sink). Short circuit protected. When current exceeds 10 mA for any channel, for > 50 ms, that channel is set to 0 V and a flag is set.
  • Update Rate: 5 µs per channel
  • ESD Protection: Designed to meet the testing requirements of IEC 801-2 Level 2. (4 kV transient with a peak current of 7.5 A and a time constant of approximately 60 ns).
  • Power: 5 VDC @ 300 mA typical (est.); ±12 VDC @ 200 mA (est. quiescent) Add 2 mA per 1 mA load per channel
  • Ground: Channel pair returns (Ch-Lo (-)) are common but are isolated (250 Vpeak) from system ground.
  • Weight: 1.5 oz. (42 g)
Block Diagram

(Click diagram to enlarge)

Documentation
11/8/2022 7:25:24 AM
11/8/2022 7:25:49 AM
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