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16 D/A Outputs (±10.0 V @ ±10 mA)

The DA2 module features 16 D/A output channels with a full scale range of ±10 VDC at ±10 mA (max). The DA2 module also offers external trigger/synchronization signal (RS422/485) capability, which provides/accepts a trigger signal to/from other module(s).

  • The module includes extensive Background Built-in-Test (BIT). In addition to output signal read-back (wrap) capabilities, overloaded outputs are detected with automatic channel shut-down protection, and the results are displayed in a status word. The modules also include D/A FIFO buffering for greater control of the output voltage and signal data. Once enabled and triggered, the D/A FIFO buffer accepts, stores, and outputs the voltage (and/or current) commands for applications requiring simulation of waveform generation (single or periodic). The output data command word is formatted as a percentage of the Full Scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.

  • Resolution: 16-bit/channel for voltage command modes.
  • Output Format: Single-ended
  • Output Range: ±10 VDC, ±5 VDC, ±2.5 VDC, 0 to 10 VDC, 0 to 5 VDC; range programmable for each channel; 10 mA max per Ch.
  • Output and Ground Impedance: < 1 Ω for each output
  • System Protection: Output is set to open circuit at reset or Power-On.
  • Linearity Error: ±0.10% FS range (FSR) over temperature
  • Offset Error: ±3 mV
  • Gain Error: ±0.10% FSR ± 0.02% x (maximum current in load (mA)), per channel. Example: The channel is expected to operate @ 2.5 mA maximum, therefore the effective gain error calculates to: (±0.10%) ± (0.02% x 2.5) = ±0.15% FSR
  • Crosstalk Error (common return): ±0.063% / FSR (V) x (the cumulative maximum ∆ current in the other 15 channel loads (mA)). Example: Seven channels @ 2.5 mA, eight channels @ 5 mA, max., @ ±10 V range, so, the error calculates to: (±0.063 / 20) * (±57.5) = ±0.18% maximum (@ FSR of ±10 V, this specific example)
  • Settling Time: 15 µs typ. (25 µs max.)
  • Data Buffer: FIFO, 1 M x 16 channels elements deep. See Operations Manual for functional details.
  • Load: Can drive a capacitive load of 0.1 µF, 10 mA/Ch max. (Source or Sink). Short circuit protected. When current exceeds 10 mA for I2T calculation, Time = TBD, that channel is set to open circuit and a flag is set.
  • Update Rate: 40 µs (25 kHz max.) per channel.
  • External Sync (pending): Module is provided with RS-485/422 transceiver for external channel output triggering and/or synchronization capabilities. (provides or accepts trigger signal from other module(s))
  • ESD Protection: Designed to meet the testing requirements of IEC 801-2 Level 2. (4 kV transient with a peak current of 7.5 A and a time constant of approximately 60 ns).
  • Power: 5 VDC @ 350 mA typical (est.); ±12 VDC @ 100 mA (est. quiescent). Add 1 mA per 1 mA load per channel ±12 VDC power supplies.
  • Ground: All channel returns (Ch-Lo (-)) are common, but are isolated (250 Vpeak) from system ground.
  • Weight: 1.5 oz. (42 g)
Block Diagram
3/22/2024 1:15:10 PM
3/22/2024 1:15:24 PM
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