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DSx (DRx)

Digital-to-Synchro or Resolver Simulation

Synchros and Resolvers are transformer-type voltage/current transducers that convert a shaft or other rotating device's angular position and/or velocity to a multi-wire AC electrical signal. Both deliver signals proportional to the Sine and/or Cosine of the shaft angle. A Digital-to-Synchro (or Digital-to-Resolver) simulator is used to convert digital angle/velocity commands to corresponding Synchro/Resolver AC signals.

A wide variety of D/S and D/R modules are available to cover the range of excitation voltages/frequency, include extensive field-parameter programmability, and provide a full operating envelope choice for simulating virtually any type Synchro or Resolver. By eliminating the need for external transformers and operating with lower AC reference frequencies, these solid-state designs offer huge space savings.

All D/S or D/R modules feature a wrap-around self-test capability and most platforms support an optional, programmable AC excitation supply. In addition to state-of-the-art technologies and design algorithms, the modules include many other useful application features such as reference voltage and frequency measurement, reference loss detection, and paired channel, two-speed operation.

There are three types of D/S and D/R Modules.

Features
  • 3 Channel Modules: These high-density modules have a lower power output drive (0.5 VA per channel, max.). The lower power output drive is ideal for driving solid-state input instruments, gauges, and Synchro Booster Amplifiers (SBAs).
  • 2 Channel Modules: The 2-channel modules have a standard power output drive (1.5 VA [2.2 VA for DSE/DRE] per channel, max.).
  • 1 Channel Modules*: The single-channel modules have a high-power output drive capability (3 VA per channel, max.).
  • *Single channel module pending - contact factory for availability.
  • All D/S and D/R modules feature a wrap-around self-test capability and most platforms support an optional, programmable AC excitation supply. In addition to state-of-the-art technologies and design algorithms, the modules include many other useful application features such as reference voltage and frequency measurement, reference loss detection, and paired channel, two-speed operation.

Specifications
  • Number of Channels: 1, 2, or 3 channels
  • Resolution: 16 bits (.0055°)
  • Output Format: Galvanic isolated. Synchro or Resolver and programmable as ratio or fixed. See Model Designations table in manual.
  • Output Voltage: 2-28 VLL (low voltage modules); 28-90 VLL (high voltage modules); 90 VLL (DS8 only).
  • Reference Voltage: 2-115 Vrms Galvanic isolated. Uses 1 mA maximum/channel.
  • Regulation (VL-L): ±5% max. No load to Full load.
  • Ratio: Dual speed, programmable, Set any ratio between 2 and 255 (two and three channel models only).
  • Phase Shift: ±0.5° maximum between output and reference @ 0° default/commanded phase, or programmable induced phase shift tolerance.
  • Self-Test: Built-in wraparound self-test
  • Settling Time: Less than 100 microseconds
  • Rotational Mode*: Angle rotation speeds up to ±9,999°/sec, single-speed or coarse channel (*Programmable; designed to meet efficacy varies on operational and application parameters.)
  • Start/Stop Mode: Produces the “Start Angle” and will rotate the output angle until the programmed “Stop Angle” is reached.
  • Valid Output Timing: Output within the output accuracy bounds within 125 ms of receiving a reference voltage input.
  • Weight: 1.5 oz. (42 g); 1.85 oz (53 g) (DSN model)
Module Specific Details

 

Module ID No. of
Channels
Full Scale Output
Voltage
(RMS VL-L)*1
Output Power/
Ch. (max)
(VA) *4
Frequency Range
(Hz)*1
Accuracy
Synchro Resolver
DS1 DR1 1*2 2-28 3 47-1k ±3.5 arc-min (0.060º)
DS2 DR2 1*2 2-28 3 1k-5k ±3.5 arc-min (0.060º)
DS3 DR3 1*2 2-28 3 5k-10k ±3.5 arc-min (0.060º)
DS4 DR4 1*2 2-28 3 10k-20k ±3.5 arc-min (0.060º)
DS5 DR5 1*2 28-90 3 47-1k ±3.5 arc-min (0.060º)
DS8 x 1 90 8 400 ±3.5 arc-min (0.060º)
DSA DRA 2 2-28 1.5 47-1k ±1 arc-min (0.0167º)
DSB DRB 2 2-28 1.5 1k-5k ±1 arc-min (0.0167º)
DSC DRC 2 2-28 1.5 5k-10k ±1 arc-min (0.0167º)
DSD DRD 2 2-28 1.5 10k-20k ±1 arc-min (0.0167º)
DSE DRE 2 28-90 2.2 47-1k ±1 arc-min (0.0167º)
DSJ DRJ 3 2-28 0.5 47-1k ±1 arc-min (0.0167º)
DSK DRK 3 2-28 0.5 1k-5k ±1 arc-min (0.0167º)
DSL x 3 2-28 0.5 5k-10k ±1 – ±3 arc-min*3
x DRL 3 2-28 0.5 5k-10k ±1 – ±2 arc-min*3
DSM DRM 3 2-28 0.5 10k-20k (contact factory)
DSN DRN 3 28-90 0.5 47-1k ±1 arc-min (0.0167º)
*1 Unless otherwise specified, expected operating parameters tolerance within ±20% for all channels.
*2 Contact factory for single channel function module availability.
*3 Accuracy maintained based on customer-specified set of operating parameters to include VLL, VREF @ FREQ (expected operating parameters tolerance within ±20% for all channels). Board-level dash number to be assigned.
*4 Output Load/Drive Power Derating:
   - For low voltage modules (2-28 VLL), the specified power is rated maximum at 28-11.8 VLL, then derates linearly from 11.8 VLL to 2 VLL.
   - For high voltage modules (28-90 VLL) the specified power is rated maximum at 90 VLL, then derates linearly to 28 VLL.

 

 Module Type  Power @
 +5 VDC
 Power @
 ±12 VDC
 Power @
 Add to ±12 VDC current
 per V.A. load per channel
 1 Channel Low Voltage*  TBD  TBD  TBD
 1 Channel High Voltage  1.88 A  190 mA  61 mA
 2 Channel High Voltage  950 mA  120 mA  57 mA
 3 Channel Low Voltage  400 mA  110 mA  113 mA
 3 Channel High Voltage  500 mA  160 mA  145 mA

 

Module Type Inrush Current @
+5VDC (Module Turn On)
Inrush Current @
+12VDC (Module Turn On)
Inrush Current @
+12VDC (Single Channel Turn On)
Inrush Current @
-12VDC (Module Turn On)
Inrush Current @
-12VDC (Single Channel Turn On)
1 Channel Low Voltage* TBD TBD TBD TBD TBD
1 Channel High Voltage* TBD TBD TBD TBD TBD
2 Channel Low Voltage ≤ 650 mA ≤ 10 mA ≤ 170 mA ≤ 10 mA ≤ 170 mA
2 Channel High Voltage TBD TBD TBD TBD TBD
3 Channel Low Voltage ≤ 400 mA N/A ≤ 120 mA N/A ≤ 120 mA
3 Channel High Voltage ≤ 2.6A ≤ 250 mA ≤ 700 mA ≤ 250 mA ≤ 700 mA

* Contact factory for single channel availability

Block Diagram
Documentation
8/26/2024 8:28:16 AM
8/26/2024 8:28:46 AM
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