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DA3

4 (High Current) D/A Outputs (±40 VDC or +100 mA)

The Digital-to-Analog (D/A) module DA3 provides 4 independent D/A output channels with a full-scale range ±40 VDC (V-control mode) and ±100 mA (I-control mode). Linearity/accuracy is ±0.10% FS range over temperature. The DA3 provides either voltage or current control loop modes, which are programmable for the application.

The DA3 module includes extensive Background Built-in-Test (BIT). In addition to output signal read-back (wrap) capabilities, overloaded outputs are detected with automatic channel shut-down protection, and the results are displayed in a status word. DA3 also include D/A FIFO buffering for greater control of the output voltage and signal data. Once enabled and triggered, the D/A FIFO buffer accepts, stores, and outputs the voltage (and/or current) commands for applications requiring simulation of waveform generation (single or periodic). The output data command word is formatted as a percentage of the Full Scale (FS) range selection, which allows maximum resolution and accuracy at lower voltage ranges.

 

Features
  • High-quality D/A conversion, 16-Bit/channel
  • Designed to meet the testing requirements of IEC 801-2 Level 2
  • Continuous background BIT
  • Automatic shutdown protection with the results displayed in a status word
  • Extended D/A FIFO buffering capabilities

Specifications
  • Resolution: 16-bit/channel for either voltage (V) or current (I) command modes.
  • Output Format: Single-ended
  • Output Range: ±40 VDC or 0 to 40 VDC (V-control mode) or ±100 mA (I-control mode), programmable.
  • Output Impedance: < 1 Ω
  • System Protection: Output is set to 0 V at reset or Power-On.
  • Linearity Error: ±0.1% FS range over temperature
  • Offset Error: ±25 mV or ±100 µA
  • Gain Error: ±0.05% FS range (derates to ±0.1% FSR from 25ºC to +85ºC)
  • Settling Time: 10 µs typical (15 µs max.)
  • Data Buffer: See Operations Manual for details.
  • Load: Can drive a capacitive load of 0.1 µF, 100 mA/Ch max. (Source or Sink). Short circuit protected. When current exceeds 100 mA for any channel, for > 50 ms, that channel is set to 0 V (mA) and a flag is set.
  • Update Rate: 5 µs per channel
  • ESD Protection: Designed to meet the testing requirements of IEC 801-2 Level 2 (4 kV transient with a peak current of 7.5 A and a time constant of approximately 60 ns).
  • Power: 5 VDC @ 450 mA typical (est.); ±12 VDC @ 250 mA (est. quiescent). Add 3.5 mA per 1 mA output load per channel.
  • Ground: All grounds are isolated. Each channel is isolated from the other three with an isolation barrier to 250V continuous. Each of the channels is also isolated from system ground with an isolation barrier of 250V continuous.
  • Weight: 2.65 oz (with heatsink)
Block Diagram

(Click diagram to enlarge)

Documentation
12/7/2021 2:29:35 PM
12/7/2021 2:27:20 PM
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