The “Modular Open Systems Approach” is an acquisition and design strategy mandated by the US Department of Defense. It promotes open standard architectures within platforms and their major system components.
The “Modular Open Systems Approach” is an acquisition and design strategy mandated by the US Department of Defense. It promotes open standard architectures within platforms and their major system components.
The Department of Defense seeks to create a more competitive environment in its supply chain. MOSA is intended to enhance competition, accelerate technology refreshes, save cost, and improve interoperability across subsystems.
MOSA requires electrical engineers to maximize reconfigurability, reuse environmental qualifications, reuse software, plan for scalability, utilize COTS Hardware, and select Future Airborne Capability Environment (FACE™) conformant operating systems.
Sensor Open Systems Architecture (SOSA™) is one of several standards that are part of the MOSA mandates. The standard favors modularity and leverages widely supported, consensus-based, nonproprietary standards for key interfaces.
The objective of SOSA™ is to unify VITA standards and army navy air force open systems standards into one open system standard.
The Future Airborne Capability Environment (FACE™) Technical Standard is intended to enhance software portability and reuse amongst military services and platforms.
It might be mistakenly assumed that all off-the-shelf solutions are created equal.A recent demonstration highlighted a case study in which a COTS mission processor with integrated platform I/O yielded SWaP improvements from the typical I/O solution provided by the usual XMC’s.
NAI’s COSA is the right solution that can support the processing and I/O requirements while reducing SWaP.
SIU33 and SIU35 chassis have different addressing schemes. This image shows the difference. Please note the relative position of the power supplies.
Temperatures are monitored on NAI motherboards and modules. These values can be accessed by using the following NAI function calls:
nai_status_t NAIAPI naibrd_GetModuleTemp(cardIndex, module, nai_module_temp_type_t moduleTempType, nai_module_temp_t *moduleTemp);
nai_status_t NAIAPI naibrd_GetMotherboardTemp(cardIndex, nai_motherboard_temp_type_t mbTempType, nai_motherboard_temp_t *mbTemp);
Desired Sample Rate = Max sample rate per channel / n (n = number of active channels per bank). Note that the number of channel per bank must be equal.
Log in as root. The default username and password is root. Next read the SATA wp register with the command memtool -32 43c10094.
If SATA wp is enabled, write a 0 to the SATA wp registers with the command memtool -32 4310094 = 0.
Use the following commands to enable an additional port:
-> ipAttach (4, "dtsec")
-> ifconfig("dtsec4 10.0.8.213 netmask 255.0.0.0 up")
Use the following Petalinux command in a console while connected to a master board: Ispci -vvv.
Follow this link for instructions: How to install the VISA driver.
All our Generation 5 boards implement 4 ethernet listeners
Each port can support multiple connections and all four ports can be operated simultaneously without threading issues. However, there is no guarantee that someone connecting to one port is not going to overwrite data written from another port or a connection on the same port. It is possible to turn off individual ports through the EEPROM, but there is currently no mechanism to restrict the number of simultaneous connections.
The AD4 provides an Open Circuit Detection feature that will pull up voltage in order to identify open channels. Make sure to tie both ends of any unused channels (+/-) to Channel 16-, referred to as the Common Mode Reference Point (CMRP; isolated from system power/ground). Tying only one end of a channel, while leaving the opposing end open, may cause Open Circuit Detection to deliver unwanted voltages to your channels in use.
If tying unused channels to the CMRP is not obtainable, then the channels may be deactivated using the Active Channels register (0x1898). Additionally, deactivating these channels will also allow you to increase your sample rate on your active channels.
Note: Each bank needs to have the same number of channels “Active” (ex: 10 Channels, 5 channels per bank).
The ADE / CME provides an Open Circuit Detection feature that will pull up voltage in order to identify open channels. Make sure to tie both ends of any unused channels (+/-) to Channel 16- (ADE) or Channel 8- (CME), referred to as the Common Mode Reference Point (CMRP; isolated from system power/ground). Tying only one end of a channel, while leaving the opposing end open, may cause Open Circuit Detection to deliver unwanted voltages to your channels in use.
There are no special ‘requirements’ for interfacing high voltage I/O to any of the specifically capable platforms/modules. However, the system integrator must be cognizant that some of the NAI Multifunction module choices are specifically designed to interface to high voltage sensors and be familiar with the overall signal layout and path. For example, 90VLL / 115 VREF synchro signals are common in a synchro position feedback system. The 75C2 card, as well as NAI’s other cPCI and VME common platforms, do have the high voltage signal capability and are fully tested and qualified within many test and embedded systems. Although the card(s) themselves are designed within proper guidelines, specification and design considerations, it is suggested that the end integrator be aware and confirm that all other system considerations (e.g. backplane/s and other wiring considerations) follow proper inter-pin and trace clearance guidelines as the card(s) may be configured with adjacent pins carrying high voltage signals. Also, the system integrator should be mindful of any specific operational environmental considerations. For example, high humidity operating conditions may influence the high voltage consideration system guidelines. If identified, system level adjacent high voltage signal interfacing concerns may be mitigated by system re-configuration(s), conformal coating options and other methods once identified.
There are no special requirements for interfacing high voltage I/O to any of the specifically capable platforms/modules. The systems integrator must be aware that some of the NAI multifunction modules are specially designed to interface with high voltage transducers. For example, 90VLL/115 VREF synchro signals are common in a synchro position feedback system.
All NAI platforms have high voltage signal capability and are fully tested and qualified with many test and embedded systems. The end integrator should confirm that all other system components (e.g. backplanes and wiring) follow inter-pin and trace clearance guidelines. The systems integrator should also be mindful of the operational environment, since factors such as high humidity may influence system behavior. High voltage signal interface concerns may be mitigated by a number of methods including system reconfiguration and conformal coating
No, the terms “auto-negotiation” and “auto-MDIX“ typically apply to the 10/100/1000Base-T (copper ports). However, each of the (4) FO ports can be configured independently by the customer in the field; it’s just a setting like any other port setting in the management console and each port can be toggled from 10 Gbps (default, from factory) to 1 Gbps (and vice-versa).
The NAI synchro/resolver connection convention is as follows:
|NAI Connection||SYN Connection||RSL Connection|
Using the ARINC 407-1 specification description, the NAI convention/connection is:
|NAI Connection||ARINC 407-1|
(Signal Voltage + maximum common mode voltage) should be < documented voltage specification
The A/D module inputs are differential in nature but not isolated from system ground. This means that the (+) and (-) legs must be referenced to a system ground.
Example: If (+) leg is at +20 V with respect to the system ground, and the (-) leg is at -20 V with respect to the same system ground, the channel will measure 40 V differential.
Any common mode voltage introduced could bring either the (+) or (-) leg out of the (common mode + signal voltage) range. This would saturate the differential operational amplifiers because the amplifiers themselves are not isolated.
MilCAN uses a software layer on top of a conventional CAN network (CAN-A / CAN-B) which we support on P6/CB1/CB3 modules.
MilCAN-A frame format is based on SAE J1939(PA/CB2) and uses 29-bit extended identifier format, defined in ISO 11898. Using a protocol type bit (bit #25), both J1939 and MilCAN can share the same bus. The software would be implemented by the user in Application Layer. Since MilCAN is used on top of CAN networks without the need for hardware additions or alterations, it can be easily integrated into existing systems to add deterministic and scheduled operation.
This is a voltage contact sensing in which the reference ground needs to be wired. However, when no current pull-up is required to measure the voltage, the VCC does not need to be supplied to this bank.
Yes, both VCC and GND are required to be supplied when using a pull-up (also GND is required for BIT).
Note: This also applies to the latest discrete I/O modules, DT1/DT4
A Software Support Kit (SSK) is supplied with all system platform-based, board level products, which includes html format help documentation defining board specific library functions and their respective parameter requirements. The RTL library is written in ANSI C for use in multiple OS platforms such as Windows XP/Vista/7/10, Linux, and VxWorks. The latest version of a board-specific SSK can be downloaded from our website on the individual product page. A Quick-Start Software Manual is also available for download where the SSK contents are detailed.
The NAI PCI (cPCI) vendor ID is 15 AC (hex).
When the Parity Disable bit is set to 0, it causes ARINC bit 32 to be treated as an odd parity bit. The transmitter calculates the ARINC odd parity bit and transmits it as bit 32. The receiver will check the received ARINC word for odd parity and will flag an error if it is not. When set to disable (1), parity generation and checking will be disabled for both the transmitter and receiver, and the ARINC bit 32 will be treated as data passing it on unchanged.
Normally yes, but please note that Built-in-Test (BIT) requires GND return to function
With a low side drive output the VCC would not be required to be connected to the bank.
When configured with high and low drive capability (push – pull) both VCC and GND must be connected to the bank. As an output (sinking current) GND must be connected. External VCC is not required.
Yes, this is correct.
During "power on", and while the board is configuring (booting), there may be spurious conditions where the D/A channel senses a "false" over-current condition. The solution is to perform a "status check" and "reset overload" as part of your initialization routine [VME64C2_DA_ResetOverload () command].
A clever implementation may be put in place while using the 2-speed capability of channel pairs to achieve much faster rotation speeds. We are discussing the 64DS1 specifically in this example, but this implementation may be utilized on any platform utilizing multi-speed capability D/S modules.
For example, a rotation velocity of 220 RPS is required. The maximum single speed rotation on any given channel is 13.6 RPS. By programming the ratio pair (CH1/CH2) into 2-speed mode, the fine (even) channel of the channel pair will rotate at the coarse (odd) channel programmed rate, multiplied by the ratio. Simply divide the required velocity (220 RPS) by maximum rate (13.6 RPS ) = 16.2 and round up to the nearest integer (17). Utilize and program the ratio 17 for the channel pair and connect to the fine channel output. The fine channel will now rotate at a velocity 17x the programmed coarse channel. For 220.0 RPS required on the fine channel, program ratio of 17 and program a velocity of 12.94 RPS.
The step size, in effect, is the ‘quantization’ of the amplitudes – they should be ‘constant’ until updated. At the speeds we are discussing, in a typical servo/resolver loop system, this quantization is negligible and effectively ‘filtered’ and should have no effect on the system. The step size will change as the rotation velocity increases.
The RTD (G4, RT1) modules can measure resistance of Thermistors and the end user has the capability to select a resistance range for each individual channel. Based on how your particular RTD responds over temperature, the end user can decide which range to select.
The 6 ARINC channels on each module can be individually programmed. Either channel can receive or transmit (not both at the same time) at 100 kHz or 12.5 kHz. The module can be populated on any multifunction platform. For example, the 64C2 is the VME motherboard that has the ability to house 6 of the ARINC-429 modules for a total of 36 ARINC-429 channels on one 64C2 motherboard.
The maximum velocity that can be tracked depends on the specific module. Please refer to the specification of your module. The velocity output (the digital word) represents a percentage of full scale where full scale is determined by the velocity scale (when the scaling can be adjusted by the user). The scaling feature (Velocity Scale Factor register) allows a user to rescale the digital velocity output word for a lower expected maximum rotation of the UUT. This, sets the full-scale output closer to what the actual device maximum rotation would be, resulting in better resolution. The scaling factor is a mathematical application after the conversion. It changes the digital output word resolution only. It does not affect accuracy.
Yes, however all function modules must be installed at the factory as part of the manufacturing process, which includes downloading of software code. The NAI function modules are not ‘stand alone’ devices such as IP modules. Each module is implemented via a DSP/FPGA combination and associated electronics, running sophisticated algorithms to generate the required function (e.g. A/D, D/A, S/D etc.). If required to add a module to an existing board, the customer can return the device via an RMA for an upgrade. There is an upgrade charge, that includes the cost of the module and installation, the documenting of the new P/N, and final acceptance testing on the board.
NAI’s flexible multifunction cards can be configured from over forty different function modules. MTBF calculations are based on a particular card configuration and are required to be calculated separately for each individual card. Please contact NAI sales/applications with the exact configuration you are interested in.
Yes, In Mailbox Receive operation mode the user sets up a filter in validation (match) memory for desired data that will be accepted into the mailbox matching the SDI+Label. The Receiver channel compares the SDI+Label of the incoming Arinc messages to the list of SDI+Labels in validation memory and if they match the incoming ARINC word (data) is stored in the Mailbox (RAM). Each ARINC channel has 1024 mailboxes, each addressed with a unique SDI+Label combination (SDI bits 8 and 9, Label bits 0 thru 7). Each mailbox only receives words containing its SDI+Label. Each mailbox is made up of 4 32-bit words (Status Word, Message, Timestamp and Match Enable). An ARINC mailbox cannot hold more than a single ARINC word at a time. In mailbox mode, the ARINC channel uses its Rx FIFO as a queue to hold SDI/Labels for which new messages have arrived. The user can poll the Rx FIFO count register then read the Rx FIFO to see which mailboxes have new messages.
NAI I/O embedded cards run through an initial “factory” calibration at the time of build. This “factory” calibration involves verifications utilizing external instruments where measurements are taken; gain/offset adjustments are calculated and may be downloaded. The initial calibration is performed and downloaded to the card's defined operating parameters (i.e., voltage/frequency, etc.). This is determined at the time of build and is defined in the full part number of the specific product. Once this calibration has been completed, full card operation and operation-calibration verification tests are performed. Other than VXI cards, our I/O cards are considered embedded-type platforms and do not fall under the same category as typical bench top instruments. These cards are designed with state-of-the-art digital signal processing techniques. Integral to the operation loop, there is built-in-testing (BIT) and “self-adjustments” where the health and operation of the card is monitored and/or adjusted (transparent to the user) to insure proper operation throughout. BIT Status is reported to the user. The card(s) rarely deviate from specification and if a card is deemed out of specification this would typically be captured by status indication, where repair is then usually required.
Calibration and/or calibration verification is up to the customer and/or end user. For those customers that wish periodic calibration verification, there are two options:
Use an A/D module that has a dedicated Sigma-Delta (or sometimes Delta-Sigma) A/D converter on each individual channel. Inherent to the Sigma-Delta design implementation is an oversampling delay on the input to produce the first digital conversion. (Subsequent data samples occur at the programmed sample rate.) At a 200 kHz sample rate, the group delay is approximately 6 samples (i.e. group delay = (6) x 5 µs = 30 µs). This cannot be reduced.
An important consideration in selecting a D/S-R converter is to make sure it has sufficient drive capability for the intended load. Drive capability is specified as VA (Volt Amperes) since actual CT’s or CDX's (Control Transformers Or Control Differential Transmitters) have an Inductive impedance. The key parameter needed to calculate required VA for the Synchro/CDX or Resolver load device is Zso. For a 3-wire Synchro, or a CDX, Zso is the equivalent impedance with two of the stator inputs tied together and measured to the third stator lead. The Zso for a given CT/RT/CDX is specified by the manufacturer. For resolver RT’s, Zso is the impedance of one of the two input stator windings.
To calculate the VA required for a Synchro CT or CDX load:
VA= ¾(VL-L)² / |Zso| Where VL-L is the D/S Line to Line output voltage and where |Zso| is the absolute value of Zso.
An example of a very common military CT is 11CT4e, Zso = 700 +j4900 and |Zso| is 4,950.
Therefore, required VA to drive an 11ct4e Synchro receiver is: VA= ¾(90)² / 4950 = .75(8100) / 4950 = 1.23.
A CDX output is usually connected to a CT. The total load on the D/S would be the sum of the CDX VA requirement and the CT VA requirement, each calculated based on their respective Zso values.
For Resolver RT loads, the calculation of VA is VA= (VL-L)² / |Zso|.
For a typical 11.8V L-L, size 08, RT, |Zso|=173, and VA = (11.8)² / 173 = 0.804 If the required VA is greater than what is available from the selected D/S, you can utilize a Synchro or Resolver Boost Amplifier. A technique in lieu of using a Boost Amplifier is a method whereby the load can be "tuned" using AC capacitors. This technique and calculations for capacitor values is detailed in the NAI Synchro Handbook Chapter 4, pages 32 & 33. The handbook is available on the NAI website, under "Application Notes" Synchro Handbook Chapter 4, pages 32 & 33.
When a ‘ratio’ value is programmed (the ratio set as the same ratio as the physical synchro or resolver under test), the ‘combined’ angle reading for both the coarse and fine channel will be calculated and presented in the fine channel output register. If the coarse channel register is read, it will provide the coarse angle measurement. If the fine channel register is read, it will have the ‘combined’ coarse/fine angle measurement, which is a more accurate representation of the coarse channel. For a more detailed explanation and examples, please read the Application Note on this subject. For GEN5 synchro/resolver measurement modules have a new “Combined” register 32-bits where the valid data is in the upper 24-bits. More information is provided in the Operations Manual.
Transmit operates in three modes: Immediate FIFO, Trigger FIFO and SCHEDULED. Schedule mode transmits ARINC data words according to a user pre-built schedule in Schedule Memory. There are various Schedule Transmit library commands that define how messages are sent from Tx Schedule Memory, for example how many messages to be sent, jumping to other address locations within schedule memory, the gap time, and how to trigger transmission, so there are various possible ways to set up a schedule. In the naibrd SSK (Software Support Kit located on our website) we have Arinc Transmit sample to indicate the methods to call in the naibrd library to configure the ARINC channel to transmit ARINC messages in FIFO or scheduled mode. This sample code in addition to the AR1 information located in the Operations Manual should provide you with enough information to calculate a schedule. The ARINC message is always 32-bit time. The gap or fixed-gap time is whatever you set it to (minimum gap time between messages is 4-bits).
No. However, the time interval between calibrations can be made relatively long. Write an “FFFF” to the appropriate cal interval register (reference operations manual pg. xxx). Note here however, that the A/D calibration occurs in the “background” and is totally transparent and seamless during normal operations. The background A/D calibration ensures that the card channels are operating at peak accuracy during the full operational envelope.
Below is a detailed explanation of how 2-speed Measurement data for Synchro/Resolver is calculated and presented: When a ‘ratio’ is programmed (the ratio is set as the same ratio as the physical Synchro or resolver under test), then the ‘combined’ angle reading for both the coarse and fine channel will be calculated and presented in the fine channel output register. If the coarse channel register is read, it will provide the coarse angle measurement. If the fine channel register is read, it will have the ‘combined’ coarse/fine angle measurement (which is a more accurate representation of the coarse channel).
For Single Speed (Ratio=1) applications, read Data High register of that channel.
For Multi-Speed (2-speed), better than 16-bit resolution is available by utilizing Data High and Data Low registers combined to determine the measured angle with up to 24-bit resolution.
First, read Data Low word, then Data High word of the two speed paired registers. The Data Low word must be read first, which ‘latches’ the Data High word – this ensures both the Data High word and Data Low word are ‘Synchronized’ regardless of the time span between word register reads
For 16-bit, single speed operation, the LSB weight is (1/((2^16)-1))*360 = 0.00550 degrees
For 17-bit, ratio of 2 multi-speed, the LSB weight is (1/((2^17)-1))*360 = 0.00274 degrees
For 18-bit, ratio of 4 multi-speed, the LSB weight is (1/((2^18)-1))*360 = 0.00137 degrees
For 19-bit, ratio of 8 multi-speed, the LSB weight is (1/((2^19)-1))*360 = 0.00068 degrees
For 20-bit, ratio of 16 multi-speed, the LSB weight is (1/((2^20)-1))*360 = 0.00034 degrees
For 21-bit, ratio of 32 multi-speed, the LSB weight is (1/((2^21)-1))*360 = 0.00017 degrees
For 22-bit, ratio of 64 multi-speed, the LSB weight is (1/((2^22)-1))*360 = 0.00008 degrees
For 23-bit, ratio of 128 multi-speed, the LSB weight is (1/((2^23)-1))*360 = 0.00004 degrees
For 24-bit, ratio of 256 multi-speed, the LSB weight is (1/((2^24)-1))*360 = 0.00002 degrees
Note: calculations rounded to nearest ten-thousandth of a degree
The procedure to read two speed angle:
Note: The DLL uses 16-bit calculation for the fine angle and since the lower byte in the fine register is ignore (don't care), the math works out correctly.
While using MBexec version 3.52.x on ARM motherboards, save ethernet speed and duplex settings in EEPROM with the following command:
Mbeeprom_util set EthA_miscSettings XXXXXXXX
The values for XXXXXXXX are below:
|1000 Mbps||100 Mbps||10 Mbps|
The discrete module channels of our product use an integrated output stage that implements FET circuit diagrams, as described in the operations manual(s). These channels can be programmed for output with multiple drive formats, or for input as either direct voltage sense or contact sense with a programmable pull-up/down current source. Each channel has two output drive FETs – high side and low side – that allow it to be set up as a current source, current sink, or push-pull output. A voltage sense circuit is present on the output side of the drive FETs for each channel, which is utilized as the input read circuit. This allows individual channels to be used as contact or direct voltage sense inputs.
Additionally, each channel has a "wrap" circuit that handles a specific channel complement while being scanned or multiplexed. The external VCC and GND applied are used for output drive switching and biasing for the drive FETs. When programmed for output, the "wrap" circuit compares the commanded output with the actual voltage read on the I/O pin against thresholds programmed to determine the state. When programmed for input, the "wrap" circuit acts as a redundant read, and both level reads must agree.
If VCC and GND are removed, this only shuts down the output drive and pull-up/down current source. The control and "wrap circuits" remain active and expect the channel(s) to be online and operational.
Built-in-test (BIT), utilizing the wrap, is typically used in an operating system, where the system is initialized, VCC and GND are applied, the loops are on, and the I/O is being operated.
When a channel is used, that channel should have the VCC and GND applied to its bank. Open banks, with the BIT wrap circuity still 'online' may product faults because the BIT circuitry is operating and is expecting the channel to be online. If channel are not used, an erroneous BIT result can occur, but since the channels are not used, BIT serves no real purpose and results should get ignored.
Yes - A fault will likely occur if the VCC is removed. BIT (Built-In-Test) serves a purpose in normal operating mode(s).
Most likely. To avoid this, mask the spare channels since the BIT status should be 'don't care' for the off-line channels.
If you're running half-duplex RS485, then you will need to wire the Tx(+/-) to the associated Rx(+/-) externally. (This connection is not handled on-board.)
The Tristate Transmit line bit does not automatically switch when configuring to half-duplex RS-485 mode. Set the appropriate bit in the Channel Control Low register (bit (D8) high (1) in the register for channels 1 (module offset + 0x0054) and 2 (module offset + 0x0058).
During power on, and while the board is configuring (booting), there may be spurious conditions where the D/A channel senses a ‘false’ overcurrent condition. The solution is to perform a status ‘check’ and “reset overload” as part of your initialization process [VME 64C2_DA_ResetOverload() command].
Yes. Our environmental specifications for all our products can be found here.
The way the DSP type II servo loop was implemented in this specific design; the internal conversion loop has a nuance as it is continually "monitoring for change” from the DPRAM commanded angle register. On initial power-up (or soft reset), all variables, including the initial angle is “zeroed”. If the initial commanded angle is “0” degrees, then there is “no change” for the loop to work from, so the loop doesn’t administer the "change from previous” variable – and occasionally, will initially output 225 or -135 as observed. The “workaround” is to program an angle one or two LSB from zero, initially. This initialization-only action will “kick-start” the loop and administer the initial “change in the variable” the loop needs. Programming one LSB (i.e., 0.0055 degrees) and then back to zero degrees is enough to “kick start” the conversion – once the loop is “kick-started,” there is no issue.
Yes, each channel is independent and can be factory configured as required. We refer to this as a "mixed" card, as opposed to all-Synchro or all-Resolver. This application would require engineering to assign a special code to the board which would spell out the details for each channel.
For example: Channels 1 to 3 D/S 11.8 V L-L at 1 KHz, with the reference signal at 24 Vrms. Channel 4 - D/R 11.8 V L-L output with 26 V 400Hz reference. The P/N for such a device would look like "75DS1-04CMF0-xx" The "M" would signify a mixed signal configuration and xx would define the combination details. This code would be uniquely assigned to a specific customer or application and not be sold to another company. Also, with this specifically configured board it is recommend that you consider an upgrade to the 2nd generation product, the 75DS2 which could duplicate all the functions of the 75DS1, with additional features and user programming flexibility.
VITA 62 defines both the mechanical and electrical requirements for COTS modules intended for the creation of modular power supplies that are compatible with VPX specifications. VITA 62 also defines the power generation requirements for the modules and 3U and 6U backplane slots that can be used for these power systems.
VITA 62 supports Single-Stage and Two-Stage power subsystem configurations.
Single-Stage is where modules receive the prime power as the input and generate the outputs required by this standard. This can be accomplished by a single unit or by multiple units in parallel depending on the overall power requirements.
Two-Stage is where the modules which generate the final regulated outputs (Final Power) receive their input from Front-End Modules via an intermediate voltage
There are four types of standard modules defined by VITA 62
Single-Stage Modules: Take in the prime power and provide the outputs required by this standard
Front-End Modules: Part of a two-stage system, whereby the Front-End unit takes in the prime power and converts it to an intermediate voltage
Back-End Modules: Also part of a two-stage system which accepts an intermediate voltage and provides the outputs required by this standard
Energy-Storage Modules: Provide Holdup time and can be either powered by the prime power or with intermediate power as a backend unit
NAI offers solutions for each of these module types
The VBAT option is part of the VITA62 power supply specification. This specification states that the power supply may either be the source of the VBAT signal or an energy storage module (such as a battery) can be used in the power supply. NAI chose to use the power supply +3.3_Aux output to provide the VBAT and not the battery. The VBAT output is intended for powering low power devices (up to 1Amp) such as a clock or a processor in sleep mode, etc. The reason one would use the VBAT output vs. the +3.3V_Aux output is because this provides a separate line to dedicate to low power needs and it has its own, separate overcurrent protection. It would not be affected by any type of overcurrent situation that may occur on the +3.3_Aux output. The intention of this output is not to connect to a battery as it would apply a lot of leakage current onto the battery and quickly discharge it. In addition, The VBAT has a re-settable fuse which if triggered will reset when load is removed.
ENABLE* and INHIBIT* are Control Inputs used to change the output status of the power supply. Dependent upon the status of these two controls the outputs can be configured:
1) To all be on
2) To all be off
3) To have just the +3.3V_Aux on with the others off
Additional information can be found in the Power Applications Notes section: Application Note, Using ENABLE* / INHIBIT* on VPX Power Supply. Link to this section is below:
FAIL* is part of VITA 62 and the intent of it is to indicate to other modules within the system that the VITA 62 power supply is enabled and that the outputs are within specification. Any condition which causes the outputs to not be within spec will cause the FAIL* to trigger. This can include an Overvoltage or an Overtemperature condition.
Current Share allows the user to connect two or more power supplies in parallel to either increase system power or provide redundancy. For units with the current share feature, there is one pin named “share” for each output that has this available. To implement the current share feature, you simply connect each of the share pins for each individual output via the system wire harness or backplane. Best practices should always be employed to minimize noise on the share pins and sense lines. To best achieve sharing, all share lines should be connected and remote sense lines need to be connected to the load. The remote sense lines from multiple power supplies should be terminated to the same single point of the load, when possible.
NAI designs utilize a proprietary algorithm to provide sharing. The algorithm uses bi-directional communication through the pins designated as “share” on the interface connector. The units will negotiate to determine a master; the remaining units will act as slaves. The master will vary the output voltage of the slaves to achieve sharing.
Remote sense is a feature which compensates up to a 0.5 VDC drop caused by the output leads. It is used by simply connecting the +Sense and –Sense signal(s) directly to the same signals that the output wires connect to at the load(s). If not using the remote sense, it is recommended that the sense lines be terminated as close to the output connector as possible.
Component derating is the practice of applying (designing in) components at lower than their maximum ratings (e.g. voltage, current and temperature). This enables the power supply to work throughout its full temperature range at full load, as well as extending a longer operating life. You do not have to “over buy” the power supply. All NAI power supplies are designed to the component derating guidelines of NAVMAT/NAVSO P-3641A.
If you are not using this feature, it is recommended that the sense lines be terminated as close to the output connector as possible. When this feature is not in use, you can expect the output voltage to be up to 0.5 VDC higher than the rated output.
All NAI power supplies are conduction cooled through either a baseplate or wedgelock/edge.
This is a TTL level signal which uses two lines (+TTL and –TTL). Leaving these two lines disconnected (floating) or connecting them to logic 0 keeps the power supply output(s) enabled at all times. Connecting these two pins to logic 1 will disable the power supply output(s). It should be noted that in order to apply this logic 1, a +5 VDC source will be needed.
NAI specializes in providing a wide variety of Modified COTS and Custom Power Supplies – including configurations that meet VME, cPCI and VPX (VITA 62) requirements - to meet the exact needs of our customers. Visit our Modified COTS Power Supplies page for more details on our design approach and Configurable Open Systems Architecture that allows customers to select from a full-feature library to create high reliability power solutions that meet their specs – with little or no NRE.
All NAI power supplies are 100% performance tested on ATE’s. Test data is stored for each unit and is available upon request. In addition to performance testing, the following tests are performed:
No, we do not provide mating connectors, however power supply specifications provide generic part numbers for mating connectors. NAI typically specifies connectors which are readily available through most parts distributors.
North Atlantic Industries generally continues to offer products as long as there is customer demand and we can continue to procure the materials to manufacture them. If it becomes necessary to discontinue an item, NAI will notify all of its customers of a lifetime buy, or we will offer a form, fit & function product replacement. Discontinued products are typically supported for two to three years.
Our standard warranty is one year. Extended warranties can be purchased on all products.
|Static IP:||AutoNeg: Yes||AutoNeg: No
Ex: mbeeprom_util set EthA_MiscSettings 00000001 for DHCP and AutoNegotiated Ethernet
Due to the inductive nature of synchros and resolvers there will be some inherent phase shift between the stator output and rotor excitation. Referring to the operations manual specifications for the 8810A or multifunction cards, under the heading "Phase Correction" or "Immediate Module Specifications", the 8810A or S/D module will correct for and operate with up to +/- 60 degrees of phase shift between the reference (excitation) source and stator output. Phase Lock Loss Status is monitored and reported to the user. The module converters employ a technique which synthesizes a perfect internal reference signal from the stator (or SIN, COS) inputs thereby reducing the phase shift to essentially 0 degrees. There is no standard for RDC's and phase shift. There is no military standard for resolver specifications. There is a standard for Synchros (Arinc 407-1). However, most technically-modern RDC's now typically incorporate the design technique of utilizing a synthesized ref. circuit to correct the phase shift.