Frequently Asked Questions (FAQ)

How do I connect my synchro/resolver to the NAI card or instrument? What is the NAI Synchro/Resolver signal convention?

The NAI synchro/resolver connection convention is as follows:

NAI Connection SYN connection RSL connection
S1 S1 SIN-
S2 S2 COS+
S3 S3 SIN+
S4 No connect COS-

I have a Synchro application where my signal outputs are defined as 'X', 'Y' and 'Z'. Where do I connect these pins using NAI's pin description 'S1', 'S2', 'S3' and 'S4'?

Using the ARINC 407-1 specification description, the NAI convention/connection is:

NAI Connection ARINC 407-1
S1 X
S2 Z
S3 Y
S4 No connect

We are integrating a 75C2 multi-function I/O 3U cPCI card with high voltage synchro (90 VLL / 115 VREF) into a system. Are there special requirements necessary to handle the high voltage I/O?

There are no special ‘requirements’ for interfacing high voltage I/O to any of the specifically capable platforms/modules. However, the system integrator must be cognizant that some of the NAI multi-function module choices are specifically designed to interface to high voltage sensors and be familiar with the overall signal layout and path. For example, 90VLL / 115 VREF synchro signals are common in a synchro position feedback system. The 75C2 card, as well as NAI’s other cPCI and VME common platforms, do have the high voltage signal capability and are fully tested and qualified within many test and embedded systems. Although the card(s) themselves are designed within proper guidelines, specification and design considerations, it is suggested that the end integrator be aware and confirm that all other system considerations (e.g. backplane/s and other wiring considerations) follow proper inter-pin and trace clearance guidelines as the card(s) may be configured with adjacent pins carrying high voltage signals. Also, the system integrator should be mindful of any specific operational environmental considerations. For example, high humidity operating conditions may influence the high voltage consideration system guidelines. If identified, system level adjacent high voltage signal interfacing concerns may be mitigated by system re-configuration(s), conformal coating options and other methods once identified.

Can you explain the statement “A/D signal voltage plus common mode voltage is xx volts. Note: A/D differential inputs must not “float”. Input source must have return path to ground.“

Signal voltage plus maximum common mode voltage should be less than the documented common voltage specification.
The A/D module inputs are differential but they are not isolated from system ground. What this means is that the (+) leg and the (-) leg must be referenced to system ground at some point in the system. For example, if the (+) leg was at +20V with respect to system ground, and the (-) leg was at -20V with respect to system ground, the channel would correctly measure 40V differential. However, any common mode voltage that was introduced (which again, is measured with respect to system ground) that could bring either the (+) or (-) leg out of the common mode plus signal voltage range, would saturate the differential operational amplifiers. This is because those amplifiers are not isolated. They run off rail voltages with the common reference at system ground.

Which NAI CAN Bus module would be utilized with the MilCAN protocol?

MilCAN uses a software layer on top of a conventional CAN network (CAN-A / CAN-B) which we support on the P6. The MilCAN-A frame format is based upon SAE J1939 (our PA module). It uses 29-bit extended identifier format defined in the ISO 11898. Using a Protocol Type bit (bit #25) both J1939 and MilCAN can share the same bus. The software would be implemented by the user in the Application Layer. As MilCAN is used on top of CAN networks without the need for hardware additions or alterations, it can be easily integrated into existing systems to add deterministic and scheduled operation.

Does NAI offer software support for its I/O Boards?

A Software Support Kit (SSK) is supplied with all system platform-based, board level products, which includes html format help documentation defining board specific library functions and their respective parameter requirements. The RTL library is written in ANSI C for use in multiple OS platforms such as Windows NT/2000/XP/Vista/7, Linux, VxWorks and other RTOS (LynxOS, Windows CE).
The latest version of a board-specific SSK can be downloaded from our website, www.naii.com in the software downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are detailed.
For other operating system support, contact factory.

When the K6 is configured as an INPUT sensing 28V or OPEN and 28V reference ground is required, is the Vcc also required?

This is a voltage contact sensing in which the reference ground needs to be wired. However, when no current pull-up is required to measure the voltage, the Vcc does not need to be supplied to this bank.

When the K6 is configured as an INPUT sensing GND or OPEN, and the Vcc is required, the Vcc must be referenced to the ground it is sensing. But is there a need to supply the reference ground to the K6 bank?

Yes, both Vcc and GND are required to be supplied when using a pull-up (also GND is required for BIT).

I need to identify an NAI card in my chassis. What is NAI’s PCI (or cPCI) vendor ID code for PCI or cPCI Card Platforms?

The NAI PCI (cPCI) vendor ID is 15AC (hex).

Does the Arinc 429/575 A4 Communications module support both auto parity calculation and host controlled parity override?

When the Parity Disable bit is set to 0, it causes ARINC bit 32 to be treated as an odd parity bit. The transmitter calculates the ARINC odd parity bit and transmits it as bit 32. The receiver will check the received ARINC word for odd parity and will flag an error if it is not. When set to disable (1), parity generation and checking will be disabled for both the transmitter and receiver, and the ARINC bit 32 will be treated as data passing it on unchanged.

When the K6 is configured as an OUTPUT providing 28V or OPEN, and the K6 bank only requires Vcc,is the reference ground required?

Possibly, however Built-In-Test (BIT) requires GND return to function.

When the K6 configured as an O/P providing GND or OPEN and the K6 bank only needs the referenced ground, is Vcc required?

With a low side drive output the Vcc would not be required to be connected to the bank.

In the general cases where the K6 is providing a voltage level as an output are both VCC and the reference ground are required?

When configured with high and low drive capability (push – pull) both Vcc and GND must be connected to the bank.

In the general cases where the K6 is sensing a voltage level as an input, is only the reference ground required?

Yes, this is correct.

Our problem is that when power is first applied to our VME chassis where the 64C2 card resides, there are times when the D/A (F1) module gets in a 'latched-in' an 'over-current' condition. There is nothing connected to the D/A outputs. When the issue occurs, the NAI diagnostics indicate that the D/A module has an 'over-current' condition via query to the 'over-current' status register and we observe that the D/A output channels 1-4 are always at 0v.

During ‘power on’, and while the board is configuring (booting), there may be spurious conditions where the D/A channel senses a ‘false’ over-current condition. The solution is to perform a ‘status check’ and ‘reset overload’ as part of your initialization routine [VME64C2_DA_ResetOverload () command].

When acting as a bus controller, a ‘timer value’ is used to set both ‘message-to-message’ and ‘minor time frame’ timing for the 1553 interface. It is word ‘6’ in the command block (Section 3.1.4) on page 35 of the 1553 programmers reference I was sent. What is the unit base of this timer value (1ms, us, etc.)? Upon looking through the Actel 1553 Handbook, it sounds like this would depend on the TCLK value you use in your hardware configuration, but I don’t see it stated anywhere in the document.

The NAI 1553 module uses a 24MHz input clock. The internal timer is based on a 16-bit counter which yields a 64 us resolution.

With regard to the Arinc 429/575 A4 communications module, and its 6 channels, what is the density per channel (i.e. Tx/Rx)?

The 6 ARINC channels on each module can be individually programmed. Either channel can receive or transmit (not both at the same time) at 100 kHz or 12.5 kHz. The module can be populated on any multifunction platform. For example, the 64C2 is the VME motherboard that has the ability to house 6 of the ARINC-429 modules for a total of 36 ARINC-429 channels on one 64C2 motherboard.

Referring to the 64DS1 Synchro/Resolver Simulation function, the spec/manual indicates a maximum rotation velocity of 13.6 RPS. My application needs to simulate a much faster spinning motor shaft with resolver output (220 RPS). Is it possible to achieve faster rotation speeds and is there any “step size” limitation?

A clever implementation may be put in place while using the 2-speed capability of channel pairs to achieve much faster rotation speeds. We are discussing the 64DS1 specifically in this example, but this implementation may be utilized on any platform utilizing multi-speed capability D/S modules.

For example, a rotation velocity of 220 RPS is required. The maximum single speed rotation on any given channel is 13.6 RPS. By programming the ratio pair (CH1/CH2) into 2-speed mode, the fine (even) channel of the channel pair will rotate at the coarse (odd) channel programmed rate, multiplied by the ratio. Simply divide the required velocity (220 RPS) by maximum rate (13.6 RPS ) = 16.2 and round up to the nearest integer (17). Utilize and program the ratio 17 for the channel pair and connect to the fine channel output. The fine channel will now rotate at a velocity 17x the programmed coarse channel. For 220.0 RPS required on the fine channel, program ratio of 17 and program a velocity of 12.94 RPS.

The step size, in effect, is the ‘quantization’ of the amplitudes – they should be ‘constant’ until updated. At the speeds we are discussing, in a typical servo/resolver loop system, this quantization is negligible and effectively ‘filtered’ and should have no effect on the system. The step size will change as the rotation velocity increases.

We are interested in a device which can read the resistance of Thermistors. We note that NAI has a function module (G4) for measuring the resistance of Resistance Temperature Devices (RTD's). Can the RTD function module also be used to measure Thermistors resistance?

Yes, the RTD (G4) module will measure the resistance of the Thermistor as long as the resistance of the Thermistor is over its operating temperature excursion and does not exceed the RTD module maximum resistance of 6500 ohms.

What is the maximum velocity that can be tracked?

The maximum velocity that can be tracked is 152.5878 rps. The velocity output (the digital word) represents a percentage of full scale where full scale is determined by the velocity scale (when the scaling can be adjusted by the user). The scaling feature (Velocity Scale Factor register) allows a user to rescale the digital velocity output word for a lower expected maximum rotation of the UUT. This, sets the full-scale output closer to what the actual device (UUT) maximum rotation would be, resulting in better resolution. The scaling factor is a mathematical application after the conversion. It changes the digital output word resolution only. It does not affect accuracy.

We are using one of NAI's multi-function boards. The board was not fully populated at the time of purchase and has a "Z0" (open-no module) position. Can we purchase additional function modules and install them on the board?

All function modules must be installed at the factory as part of the manufacturing process, which includes downloading of software code. The NAI function modules are not ‘stand alone’ devices such as IP modules. Each module is implemented via a DSP/FPGA combination and associated electronics, running sophisticated algorithms to generate the required function (e.g. A/D, D/A, S/D etc.). If required to add a module to an existing board, the customer can return the device via an RMA for an upgrade. There is an upgrade charge, that includes the cost of the module and installation, the documenting of the new P/N, and final acceptance testing on the board.

I notice that NAI does not publish any MTBF information. How do I obtain this information?

NAI’s flexible multi-function cards can be configured from over twenty different function modules. MTBF calculations are based on a particular card configuration and are required to be calculated separately for each individual card. Please contact NAI sales/applications with the exact configuration you are interested in.

With regard to the Arinc 429/575 A4 communications module, does the "receive" function support label + sdi data steering and does it store at least 1024 data words?

Receive Operation: In mailbox mode, received ARINC words are stored in mailboxes or records that are indexed by the SDI/Label of the ARINC word. There is one mailbox allocated for each SDI/Label combination. Each Receive FIFO size is 255 X 32 and each Transmit FIFO size is 255 X 32.

We are considering using NAI's 75DS1 board for simulating both Synchro and Resolver outputs. Is this possible on one board? Can the four-channel unit be configured with a combination of both Synchro and Resolver outputs?

Yes, each channel is independent and can be factory configured as required. We refer to this as a "mixed" card as opposed to all Synchro or all Resolver. To accomplish this, application engineering must assign a special code to the board which will spell out the details for each channel. For example - channels 1 to 3 D/S 11.8 V L-L at 1 KHz, with ref. signal at 24 V rms. Channel 4 - D/R 11.8 V L-L output with 26 V 400Hz reference. The P/N for such a device would look like ‘75DS1-04CMF0-xx’ where the ‘M’ signifies mixed signal configuration and ‘xx’ would define the combination details. This code is uniquely assigned for a customer/application and will not be sold to any other Company.

Do I need to, and if so, when should I “calibrate” my card?

NAI I/O embedded cards run through an initial “factory” calibration at the time of build. This “factory” calibration involves verifications utilizing external instruments where measurements are taken; gain/offset adjustments are calculated and may be downloaded. The initial calibration is performed and downloaded to the card's defined operating parameters (i.e., voltage/frequency, etc.). This is determined at the time of build and is defined in the full part number of the specific product. Once this calibration has been completed, full card operation and operation-calibration verification tests are performed.

The cards are designed with state-of-the-art digital signal processing techniques. Integral to the operation loop, there is built-in-testing (BIT) and “self-adjustments” where the health and operation of the card is monitored and/or adjusted (transparent to the user) to insure proper operation throughout the operating envelope of the instrument.

Calibration verification is up to the customer and/or end user. NAI recommends yearly calibration verification. For those customers that wish periodic calibration verification, two options are open:

  1. Customers may perform their own calibration verification routines comparing test results to the published specifications of the instrument.
  2. NAI can provide a periodic calibration verification service for an associated fee to ensure the card performs within specifications. NAI would provide a calibration certificate traceable to NIST standards and test data.

As an aside, the card(s) rarely deviate from specification. If a card is deemed out of specification, repair is usually required.

Are there limits to the amount of phase shift possible (between the reference source and signal inputs from a synchro or resolver) connected to the API 8810A or Multifunction card S/D module? Also with regard to electronics that are not for bench top use, do you know of a standard or document(s) that describe limits for phase shifts of RDC's, specific for synchros and resolvers?

Referring to the operations manual specifications for the 8810A or multi-function cards, under the heading "Phase Correction" or "Immediate Module Specifications", the 8810A or S/D module will correct for and operate with up to +/- 60 degrees of phase shift between the ref. input and the stator outputs. The module converters employ a technique which synthesizes a perfect internal reference signal from the stator (or SIN, COS) inputs thereby reducing the phase shift to essentially 0 degrees.

Are there limits to the amount of phase shift possible (between the reference source and signal inputs from a synchro or resolver) connected to the API 8810A or Multifunction card S/D module? Also with regard to electronics that are not for bench top use, do you know of a standard or document(s) that describe limits for phase shifts of RDC's, specific for synchros and resolvers?

Referring to the operations manual specifications for the 8810A or multi-function cards, under the heading "Phase Correction" or "Immediate Module Specifications", the 8810A or S/D module will correct for and operate with up to +/- 60 degrees of phase shift between the ref. input and the stator outputs. The module converters employ a technique which synthesizes a perfect internal reference signal from the stator (or SIN, COS) inputs thereby reducing the phase shift to essentially 0 degrees. There is no standard for RDC's and phase shift. There is no military standard for resolver specifications. There is a standard for Synchros (Arinc 407-1). It's a free-for-all among the resolver manufacturers! However, most technically-modern RDC's now typically incorporate the design technique of utilizing a synthesized ref. circuit to correct the phase shift.

I want to use NAI A/D modules for real-time control application, so low-latency is critical. Is there any way to reduce group converter delay?

The A/D module employs an individual Sigma-Delta (or sometimes Delta-Sigma) A/D converter on each channel. Inherent to the Sigma-Delta design implementation is an oversampling delay on the input to produce the first digital conversion. (Subsequent data samples occur at the programmed sample rate.) At a 200 KHz sample rate, the group delay is approximately 6 samples (i.e. group delay = (6) x 5us = 30 us). This cannot be reduced.

Regarding your D/S or D/R converter function modules, you specify a 'VA' output capability. I assume 'VA' stands for Volt Amperes. For a given load (Synchro or Resolver), how do I calculate the required output load 'VA' power requirements?

An important consideration in selecting a D/S-R converter is to make sure it has sufficient drive capability for the intended load. Drive capability is specified as VA (Volt Amperes) since actual CT’s or CDX's (Control Transformers Or Control Differential Transmitters) have an Inductive impedance. The key parameter needed to calculate required VA for the Synchro/CDX or Resolver load device is Zso. For a 3-wire Synchro, or a CDX, Zso is the equivalent impedance with two of the stator inputs tied together and measured to the third stator lead. The Zso for a given CT/RT/CDX is specified by the manufacturer. For resolver RT’s, Zso is the impedance of one of the two input stator windings.

To calculate the VA required for a Synchro CT or CDX load, see the following:

VA= ¾(VL-L)² / |Zso| Where VL-L is the D/S Line to Line output voltage and where |Zso| is the absolute value of Zso.

An example of a very common military CT (11CT4e) Zso is 700 +j4900 and |Zso| is 4,950 ?:

Therefore, required VA to drive an 11ct4e Synchro receiver is: VA= ¾(90)² / 4950 = .75(8100) / 4950 = 1.23

A CDX output is usually connected to a CT. The total load on the D/S would be the sum of the CDX VA requirement and the CT VA requirement, each calculated based on their respective Zso values.

For Resolver RT loads, the calculation of VA is: VA= (VL-L)² / |Zso|

For a typical 11.8V L-L, size 08, RT, |Zso|=173? VA = (11.8)² / 173 = 0.80M

Finally, if the required VA is greater than what is available from the selected D/S, a technique can be used to reduce the load VA. This is a method whereby the load can be "tuned" using AC capacitors. This technique and calculations for capacitor values is detailed in the NAI Synchro Handbook Chapter 4, pages 32 & 33. The handbook is available on the NAI website, under "Application Notes" (http://www.naii.com/secure/files/synchrohandbookch_4_Rev%20A.pdf?userID=8262&ipAddress=167.206.187.68 )

Regarding newer platforms with A/D modules, can you completely disable background ADC calibration? (Want to perform this only during initialization.)

No. However, the time interval between calibrations can be made relatively long. Write an “FFFF” to the appropriate cal interval register (reference operations manual pg. xxx). Note here however, that the A/D calibration occurs in the “background” and is totally transparent and seamless during normal operations. The background A/D calibration ensures that the card channels are operating at peak accuracy during the full operational envelope.

How is 2-Speed measurement data for synchro/resolver calculated and presented. Can you expand on the 2-speed operation with some examples?

This is how two-speed works in S/D. When a ‘ratio’ is programmed (the ratio is set as the same ratio as the physical synchro or resolver under test), the ‘combined’ angle reading for both the coarse and fine channel will be calculated and presented in the fine channel output register. If the coarse channel register is read, it will provide the coarse angle measurement. If the fine channel register is read, it will have the ‘combined’ coarse/fine angle measurement, which is a more accurate representation of the coarse channel. For a more detailed explanation and examples, please read an Application Note on this subject

We are interested in a device which can read the resistance of Thermistors. We note that NAI has a function module (G4) for measuring the resistance of Resistance Temperature Devices (RTD's). Can the RTD function module also be used to measure Thermistors resistance?

Yes, the RTD (G4) module will measure resistance of Thermistors as long as the resistance (of the Thermistor) over it's operating temperature excursion does not exceed the RTD module maximum resistance of 6500 ohms.

Does the Arinc 429/575 A4 communications module, for the transmit function support frame scheduling, where individual 429 labels (data words) are scheduled at a desired rate? Does it support label + sdi scheduling?

Transmit operates in three modes: Immediate FIFO, Trigger FIFO and SCHEDULED. Schedule mode transmits ARINC data words according to a pre-built schedule in Schedule Memory. In that table there are various commands that define what messages are sent and at what rate they are to be transmitted. There are various possible ways to set up a schedule.

I read the manual but I still don’t understand how 2-Speed Measurement data for Synchro/Resolver is calculated and presented. Can you expand on the 2-speed operation with some examples?

Below is a detailed explanation of how 2-speed Measurement data for Synchro/Resolver is calculated and presented:

When a ‘ratio’ is programmed (the ratio is set as the same ratio as the physical Synchro or resolver under test), then the ‘combined’ angle reading for both the coarse and fine channel will be calculated and presented in the fine channel output register. If the coarse channel register is read, it will provide the coarse angle measurement. If the fine channel register is read, it will have the ‘combined’ coarse/fine angle measurement (which is a more accurate representation of the coarse channel).

For Single Speed (Ratio=1) applications, read Data High register of that channel.

For Multi-Speed (2-speed), better than 16-bit resolution is available by utilizing Data High and Data Low registers combined to determine measured angle with up to 24-bit resolution.

First read Data Low word, then Data High word of the two speed paired registers. The Data Low word must be read first, which ‘latches’ the Data High word – this ensures both the Data High word and Data Low word are ‘Synchronized’ regardless of time span between word register reads.

The paired registers are Ch1 Data Hi/Ch2 Data Lo, Ch3 Data Hi/Ch4 Data Lo and CH5 Data Hi/Ch6 Data Lo.

For 16-bit, single speed operation, the LSB weight is (1/((2^16)-1))*360 = 0.00550 degrees
For 17-bit, ratio of 2 multi-speed, the LSB weight is (1/((2^17)-1))*360 = 0.00274 degrees
For 18-bit, ratio of 4 multi-speed, the LSB weight is (1/((2^18)-1))*360 = 0.00137 degrees
For 19-bit, ratio of 8 multi-speed, the LSB weight is (1/((2^19)-1))*360 = 0.00068 degrees
For 20-bit, ratio of 16 multi-speed, the LSB weight is (1/((2^20)-1))*360 = 0.00034 degrees
For 21-bit, ratio of 32 multi-speed, the LSB weight is (1/((2^21)-1))*360 = 0.00017 degrees
For 22-bit, ratio of 64 multi-speed, the LSB weight is (1/((2^22)-1))*360 = 0.00008 degrees
For 23-bit, ratio of 128 multi-speed, the LSB weight is (1/((2^23)-1))*360 = 0.00004 degrees
For 24-bit, ratio of 256 multi-speed, the LSB weight is (1/((2^24)-1))*360 = 0.00002 degrees
Note: – calculations were rounded to nearest ten-thousandth of a degree

Example:

• Two speed ratio = 16:1 (channel pair defined as CH3, CH4)
• Two speed channel pair CH4 Hi/CH4 Lo
• CH3 HI = 0x0800 (not required for two speed)
• CH4 HI = 0x0800
• CH4 Lo = 0xE3E0 (only the upper byte(E3) is used, ignore the lower byte(E0) in the calculation.

The procedure to read two speed angle:

1. Read CH4 Lo register which is 0xE3E0 in the example case.
2. Read CH4 Hi register which is 0x0800 in the example case.
3. Calculate the two-speed combined angle by concatenating the data from CH4 HI and CH4 Lo registers. So, we have 0x800E3 and its decimal number is 524515. Two speed angle = (524515/((2^24)-1))*360 = 11.25487 degrees. This is the combined two speed angle and is providing up to 20 bit of resolution (ratio 16:1).

In NAI (typical) DLL, PC73SD4_GetTwoSpeedAngle, (example) the two speed angle is calculated as // Read Angle High Resolution Lower 16 Bit Word binAngle = PC73SD4_READREG_ISA( Card, AngHresReg[(Channel/2)-1][PAGE], AngHresReg[(Channel/2)-1][OFFSET] ); tempAngle = (double)(0xffff & binAngle) * BIT16/65536.0; binAngle = PC73SD4_READREG_ISA( Card, AngleReg[Channel-1][PAGE], AngleReg[Channel-1][OFFSET] ); // Convert Angle to double *Angle = tempAngle + (double)(0xffff & binAngle) * BIT16;

Where BIT16 is defined as 0.0054931640625.

The math in the DLL yielded the following:

1. Read the two speed pair low data = 0xE3E0 = 58336 * 0.005493164 / 65536 = 0.004889.
2. Read the two speed pair high data = 0x800 = 2048 * 0.005493164 = 11.249999872
3. Add the combined angle = coarse + fine = 11.249999872+0.004889 = 11.254888872

Note: the .dll uses 16 bit calculation for the fine angle and since the lower byte in the fine register is ignore (don’t care), the math works out correctly.

How does the discrete module (K2, K3, and K6) generally operate?

The discrete module channels utilize an integrated output stage which implements the FET circuit diagrams as depicted in the operations manual(s). The channels can be programmed for output with multiple drive format capability, or input either direct voltage sense or contact sense with a programmable pull up/down current source. There are two output drive FETs – high side and low side. This allows the individual channel, when programmed as an ‘output’, to be set up as a high-side drive (current source), a low-side drive (current sink), or a push pull (current source when output is programmed ‘on’ or a current sink when output is programmed ‘off’). On the output side of the drive FETs is a voltage sense circuit for each channel which is utilized as the “input’ read circuit. This allows the individual channel, when programmed as input, to act as a contact or direct voltage sense. There are also “wrap” circuits which are used for redundant comparisons. Each “wrap” circuit handles a particular channel compliment as each channel is scanned/multiplexed. The external VCC and GND applied is utilized for the output drive switching and biasing for the drive FETs.

When programmed for an output, the “wrap” compares the commanded output with actual voltage read on the I/O pin (against thresholds programmed to determine state). When programmed for an input, the “wrap” acts as a redundant read – both level reads must agree.

If VCC and GND is removed, this only shuts down the output drive and pull up/down current source. The control and “wrap circuits” are still ‘alive’ and expect the channel(s) to be on line and operational (with VCC/GND)

Background built-in-test (BIT), utilizing the wrap, is typically utilized in an ‘operating’ system, where the system is initialized, VCC and GND has been applied, the ‘loops’ are on, and I/O is being operated.

Regarding discrete module (K2, K3 and K6), do all Vcc points need to be wired to prevent board faults?

If the channel is being used, it should have the VCC and GND applied to the bank. Open banks, with the BIT wrap circuitry still ‘on-line’, may produce faults because the BIT circuitry is operating and is expecting the channel to be on-line. If channels are not being used, you could have erroneous BIT, but since the channels are not used, BIT serves no real purpose.

Regarding discrete module (K2, K3 and K6), if a VCC point is switched between 0VDC and 24VDC from the power supply, should we expect a fault?

Yes – you would most likely receive a fault if the VCC is removed. BIT serves its purpose in normal operating mode(s).

Regarding discrete module (K2, K3 and K6), if a VCC point it left floating (spare bank), should we expect a fault?

Most likely. You could mask spare channels since the BIT status should be “don’t care” because the channel is “off-line”.

I can’t seem to get the serial channels operating properly in half-duplex mode, where I only have one twisted pair for both the TX and RX differential signals.

If you're running half-duplex RS485, then you will need to wire the Tx(+/-) to the associated Rx(+/-) externally. (This is not handled on-board.)

The Tristate Transmit line bit does not automatically switch when configuring to half-duplex RS-485 mode. Set the appropriate bit in the Channel Control Low register (bit (D8) high (1) in the register for channels 1 (module offset + 0x0054) and 2 (module offset + 0x0058).

When power is first applied to our VME chassis where the NAI Multifunction I/O Board resides, the D/A module sometimes gets in a latched over-current condition. There is nothing connected to the D/A outputs. When the issue occurs, the NAI diagnostics indicate that the D/A module has an over-current condition via query to the over-current status register and we observe that the D/A output channels 1-4 are always at 0v.

During power on, and while the board is configuring (booting), there may be spurious conditions where the D/A channel senses a ‘false’ over-current condition. The solution is to perform a status ‘check’ and “reset overload” as part of your initialization process [VME64C2_DA_ResetOverload() command].

Does NAI publish the Environmental Specifications that its boards are designed to?

Yes. Please read the following Application Note outlining the Environmental Specifications for all Board level products.

Why does my 75DS1 (with both synchro or resolver format modules) occasionally output either 225 degrees or -135 degrees on initial command of 0 degrees?

The way the DSP type II servo loop was implemented in this specific design; the internal conversion loop has a nuance as it is continually "monitoring for change” from the DPRAM commanded angle register. On initial power up (or soft reset), all variables, including the initial angle is “zeroed”. If the initial commanded angle is “0” degrees, then there is “no change” for the loop to work from, so the loop doesn’t administer the "change from previous” variable – and occasionally, will initially output 225 or -135 as observed. The “workaround” is to initially program any angle command other than 0 degrees. This initialization-only action will “kick start” the loop and administer the initial “change in variable” the loop needs. Programming 1 lsb (i.e. 0.0055 degrees) and then back to zero degrees is enough to “kick start” the conversion – once the loop is “kick started”, there is no issue.

We are considering using NAI's 75DS1 board for simulating both Synchro and Resolver outputs. Is this possible on one board? Can the four channel unit be configured with a combination of both Synchro and Resolver outputs?

Yes, each channel is independent and can be factory configured as required. We refer to this as a "mixed" card, as opposed to all-Synchro or all-Resolver. This application would require engineering to assign a special code to the board which would spell out the details for each channel. For example: Channels 1 to 3 D/S 11.8 V L-L at 1 KHz, with ref. signal at 24 V rms. Channel 4 - D/R 11.8 V L-L output with 26 V 400Hz reference. The P/N for such a device would look like "75DS1-04CMF0-xx" The "M" would signify a mixed signal configuration and xx would define the combination details. This code would be uniquely assigned for a customer or application and would not be sold to any other company. Also, it would be suggested that you consider an upgraded, 2nd generation product, the 75DS2 which could duplicate all the functions of the 75DS1, with additional features and user programming flexibility.

It is suggested that you consider a newer 2nd generation product (75DS2) which can duplicate all the functions of the 75DS1 with more functionality and user programming flexibility.

In VITA 62 (VPX) power supplies, what is the VBAT signal and how would I use it?

The VBAT option is part of the VITA62 power supply specification. This specification states that the power supply may either be the source of the VBAT signal or an energy storage module (such as a battery) can be used in the power supply. NAI chose to use the power supply +3.3_Aux output to provide the VBAT and not the battery. The VBAT output is intended for powering low power devices (up to 1Amp) such as a clock or a processor in sleep mode, etc. The reason one would use the VBAT output vs. the +3.3V_Aux output is because this provides a separate line to dedicate to low power needs and it has its own, separate overcurrent protection. It would not be affected by any type of overcurrent situation that may occur on the +3.3_Aux output. The intention of this output is not to connect to a battery as it would apply a lot of leakage current onto the battery and quickly discharge it. In addition, The VBAT has a re-settable fuse which if triggered will reset when load is removed.

How do the outputs VS1-VS3 behave when the sense lines go either high impedance or short?

When the sense lines are open, the voltage will increase…typically, the limits are as follows: VS1 ~ +12.600, VS2 ~ +3.465 and VS3 ~ +5.250, so the expected increase in voltage would not exceed these numbers. In the case of a short, the O/V will latch and the output would have to be reset.

What is your
warranty policy?

Our standard warranty is one year. Extended warranties can be purchased on all products.

What is the Current Share Feature and how do I implement it?

Current share is a bi-directional bus which allows the user to connect two or more power supplies in parallel to either increase system power or provide redundancy. For units with the "current share" feature, there is one pin named “share” for each output that has this available. To implement the current share feature, you simply connect each of the share pins for each individual output via the system wire harness or backplane.

What is the purpose of Remote Sense and how do I use it?

Remote sense is a feature which compensates up to a 0.5Vdc drop caused by the output leads. It is used by simply connecting the +Sense and –Sense signal(s) directly to the same signals that the output wires connect to at the load(s). If not using the remote sense, it is recommended that the sense lines be terminated as close to the output connector as possible.

What is component derating and how does it benefit the product?

Component derating is the practice of applying (designing in) components at lower than their maximum ratings (e.g. voltage, current and temperature). This enables the power supply to work throughout its full temperature range at full load, as well as extending a longer operating life. You do not have to “over buy” the power supply. All NAI power supplies are designed to the component derating guidelines of NAVMAT/NAVSO P-3641A.

What type of acceptance testing is performed on NAI power supplies?

All NAI power supplies are 100% performance tested on ATE’s. Test data is stored for each unit and is available upon request. In addition to performance testing, the following tests are performed:
  • Temperature Cycle testing is performed per NAVMAT guidelines on all of our products. This test is typically run for twelve cycles. Units are placed under full load and are cycled to the cold and hot temperature extremes, powered up at each extreme, monitored and data logged.
  • Random Vibration is performed using a NAVMAT profile at 6 G's, one axis which is normal to the mounting plane. Vibration on our standard products is performed on an AQL basis, or for an associated fee on a 100% basis.

What if I am not able to find exactly what I am looking for in your standard product offerings?

NAI specializes in customizing and repackaging our COTS (Commercial Off the Shelf) power supplies to suit the exact needs of our customers. You can Contact NAI through our message board or by phone. Also, you can use our “Configure Your Power Supply" tool and one of our experts will get back to you as soon as possible.

What is your general product obsolescence policy?

North Atlantic Industries generally continues to offer products as long as there is customer demand and we can continue to procure the materials to manufacture them. If it becomes necessary to discontinue an item, NAI will notify all of its customers of a lifetime buy, or we will offer a form, fit & function product replacement. Discontinued products are typically supported for two to three years.

If I choose not to use Remote Sense, how do I connect the unit and what results should I expect?

If you are not using this feature, it is recommended that the sense lines be terminated as close to the output connector as possible. When this feature is not in use, you can expect the output voltage to be up to 0.5Vdc higher than the rated output.

How do I cool NAI power supplies?

All NAI power supplies are conduction cooled through either a baseplate or wedgelock/edge.
  • On baseplate cooled versions, the power supply should be mounted to a metal surface (preferably aluminum) via the mounting screws shown on the specification outline diagram. This metal surface needs to be as flat as possible. It is also recommended that a thermal pad be used to assist with the thermal transfer.
  • On the wedgelock cooled versions, install the power supply into the card slot and ensure that the wedgelocks are tightened, making good contact with the card guides.
  • It is also important to note that for both versions the specified power supply operating temperature and loads are not exceeded.

How do I use the Remote Turn On/Off feature?

This is a TTL level signal which uses two lines (+TTL and –TTL). Leaving these two lines disconnected (floating) or connecting them to logic 0 keeps the power supply output(s) enabled at all times. Connecting these two pins to logic 1 will disable the power supply output(s). It should be noted that in order to apply this logic 1, a +5Vdc source will be needed.

Do you provide mating connectors with your power supplies?

No, we do not provide mating connectors, however power supply specifications provide generic part numbers for mating connectors. NAI typically specifies connectors which are readily available through most parts distributors.

Do your AC/DC power supplies accept both a 115Vac input and a 230Vac input?

Yes, there are two types of inputs:
  • Autosensing - Accepts an input of 115Vac to 230Vac (±10%) automatically
  • Non-Autosensing – Requires the input to the unit to be configured based on the AC input.

Do your power supplies have adjustable outputs?

NAI standard products do not have adjustable outputs. They are factory set to fixed values. If you have special needs, please contact the sales manager for your area or visit the “Configure Your Power Supply” section of our website.

What is ANSI/VITA signaling which is on most of your VME power supplies?

ANSI/VITA signaling is a standard set of three power supply signals used in VME systems. This set of signals includes:
  • AC Fail - A signal from the power supply indicating status of input
  • Sys Reset – A signal from the power supply indicating reset in progress (Ex. During power up)
  • Reset – An input to the power supply via a switch which resets the system without needing to power off.

What is the difference between the “M” COTS Mil Type and the “H” Full Mil Reliability levels on the brick products?

The difference is in the component selection. The “H” version uses Hi Rel power semiconductors (when available), and the “M” version uses plastic, encapsulated semiconductors. Both versions meet all the same temperature ranges and Mil-Std’s. The “H” version results in slightly better MTBF numbers, but may add to cost and delivery time.